ASIC Engineering Manager

Meta is seeking an Application-Specific Integrated Circuit (ASIC) Design Engineering Manager to lead our team in developing processing blocks for a System-on-Chip (SOC). As a key leader, you will drive Register-Transfer Level (RTL) design planning and execution, foster innovative methodologies, and manage IP design and SOC integration. You will collaborate closely with cross-functional teams, including Architecture, Software/Firmware, Verification, Modeling, Emulation, and Post-Silicon Validation, to shape silicon architecture and micro-architecture development.

B.S. degree in Computer Engineering, Electrical Engineering, or a relevant technical field (or equivalent practical experience) 8+ years of ASIC/SoC RTL design experience 3+ years of People Management experience In-depth understanding of RTL design tools, including Synopsys DC compiler, Cadence LEC, and Spyglass Proven track record of first-pass success in ASIC Development Experience managing multiple projects, prioritizing tasks, and collaborating with stakeholders Prior experience with interpreting functional specs and create comprehensive u-Architectures End to end SOC execution experience Hands-on RTL coding experience Post silicon support experience Understanding of high speed protocols like Ethernet/PCIe/USB

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