Design Verification Engineer

Reality Labs focuses on delivering Meta's vision through AI-first devices that leverage our wearable technologies. The compute performance and power efficiency requirements require custom silicon. We are driving the state-of-the-art forward with highly integrated SoCs that leverage breakthrough work in computer vision, machine learning, mixed reality, graphics, displays, sensors, and new ways to map the human body. Our chips will enable Meta’s Wearable devices that blend our real and virtual worlds throughout the day. We believe the only way to achieve our goals is to look at the entire stack, from transistors, through architecture, firmware, and algorithms.

Currently has, or is in the process of obtaining a Bachelor's degree in Computer Science, Computer Engineering, relevant technical field, or equivalent practical experience. Degree must be completed prior to joining Meta 2+ years of hands-on experience in SystemVerilog/UVM methodology or C/C++ based verification 2+ years experience in block/IP/sub-system and/or SoC level verification based on SystemVerilog UVM/OVM based methodologies Experience in EDA tools and scripting (Python, TCL, Perl, Shell) used to build tools and flows for verification environments Experience with revision control systems like Mercurial(Hg), Git or SVN Experience in architecting and implementing Design Verification infrastructure and executing the full verification cycle Experience in development of Universal Verification Methodology (UVM) based verification environments from scratch Experience verifying ARM/RISC-V based sub-systems and SoCs Experience verifying CPU/GPU designs Experience in one or more of the following areas: SystemVerilog Assertions (SVA), Formal, and Emulation Track record of 'first-pass success' in Application-Specific Integrated Circuit (ASIC) development cycle

Apply Now 🚀

Opens in a new tab